Crafted to expedite system design and propel the advancement of AI-driven computing, the XConn “Apollo” CXL 2.0 switch has emerged as the benchmark solution that stands as the industry first and only. It caters to environments seeking to capitalize on a CXL Memory Pool, aiming to eliminate conventional memory constraints and redefine memory architecture. This interconnect stands as the cornerstone of systems and solutions developed throughout the CXL ecosystem, featuring partners such as Samsung, Montage, Micron, and numerous others.

“XConn is proud to be at the center of the CXL movement, delivering the interconnect technology necessary to make the adoption of CXL a reality,” said Gerry Fan, CEO, XConn. “Now, as we roll out our early production samples, XConn is demonstrating the power of CXL in practice so that system manufacturers across the industry can seamlessly integrate CXL into their solutions for AI workloads.”

“Samsung has developed an integrated solution (CMM-B) to deliver the power of CXL to support the demanding memory requirements of next-generation applications with XConn CXL switch SoC,” said Dr. Sungwook Ryu, Head of Samsung Semiconductor Memory Solutions Lab. “It further underscores our belief in the CXL specification for higher performance computing with reduced software stack complexity and lower overall system cost.”

“XConn’s groundbreaking work in CXL interconnect technology is crucial for propelling computing capabilities, especially in the realm of data pooling and aggregation,” highlighted Stephen Tai, President of Montage Technology. “Aligned with the entire CXL community, we are steadfast in our commitment to advancing CXL’s adoption as the pivotal technology driving an AI-centric future.”

“With the increasing use and evolution of AI, the need for memory-centric data infrastructure becomes ever more vital,” said Charles Fan, CEO and co-founder, MemVerge. “CXL technology is transforming the industry with memory fabric for the future of computing. The combination of Memory Machine X and the innovative XConn Apllo switch makes scalable memory capacity a reality for tomorrow’s generation of AI applications.”

The XConn Apollo switch is innovative in its design, offering system developers the opportunity to future-proof devices to capitalize on the breakthrough performance of new CXL interconnect technology with the industry first and only CXL 2.0 switch, while also supporting PCIe 5.0 standards. Both PCIe and CXL can now be supported in a single design. With 2,048 GB/s of total bandwidth and 256 lanes, the chip offers unprecedented flexibility for system designers that want to capitalize on JBOG (Just-a-Bunch-Of-GPUs) and JBOA (Just-a-Bunch-Of-Accelerators) processing configurations.

Available now in early production samples, XConn Apollo delivers full support for CXL 2.0, is backwards compatible with CXL 1.1 and supports PCIe Gen 5 in hybrid mode. For the industry first and only CXL 2.0 interconnect solution sample and/or Apollo reference board, visit the website here.

Related News:

XConn Apollo Interconnect Solution Showcased at TSMC 2024

The XConn Apollo Switch Releases Early Production Samples

The post Industry First and Only CXL 2.0 Interconnect Solution at CXL DevCon 2024 appeared first on Digital IT News.

As the industry’s first and only hybrid CXL 2.0 and PCIe Gen 5 interconnect solution, the XConn Apollo switch is purpose-built to simplify the system designer process with versatile expansion and heterogeneous integration for a mix of accelerators and fault tolerance with the redundancy mission-critical applications require for true processing availability. This makes the Apollo interconnect solution ideal for use in high demand artificial intelligence (AI) application environments.

XConn has been working closely with TSMC, the world’s leading dedicated foundry, to make its XConn Apollo on TSMC’s industry leading process technologies from N16 to N5. “TSMC’s robust manufacturing and efficient project management for timely delivery enable us to sharply focus on our product design and technology development,” said Gerry Fan, President and CEO of XConn Technologies. “TSMC is our trusted foundry partner that helps us deliver our industry leading connectivity product to meet the ever-growing demands in the AI and computing markets.”

“TSMC is committed to partnering with innovators like XConn to advance their next generation interconnect technology,” said Lucas Tsai, Senior Director of Market Development and Emerging Business Management, TSMC North America. “Our industry-leading technologies and manufacturing excellence enable XConn to accelerate their chip innovation and to facilitate the rapid growth in data transmission that comes with the AI boom.”

The Apollo switch is innovative in its design, offering system developers the opportunity to future-proof devices to capitalize on the breakthrough performance of new CXL interconnect technology with the industry’s first CXL 2.0 switch, while also supporting PCIe 5.0 standards. Both PCIe and CXL can now be supported in a single design. With 2,048 GB/s of total bandwidth and 256 lanes, the chip offers unprecedented flexibility for system designers that want to capitalize on JBOG (Just-a-Bunch-Of-GPUs) and JBOA (Just-a-Bunch-Of-Accelerators) processing configurations.

Available now in production samples, XConn Apollo delivers full support for CXL 2.0, is backwards compatible with CXL 1.1 and supports PCIe Gen 5 in hybrid mode. For customer samples and/or Apollo reference boards, or to learn more about XConn’s interconnect solution, visit the XConn website here.

Related News:

The XConn Apollo Switch Releases Early Production Samples

Composable Memory Solution Featured at SC23 by XConn and Liqid

The post XConn Apollo Interconnect Solution Showcased at TSMC 2024 appeared first on Digital IT News.

The XConn Apollo switch is the industry’s first and only hybrid CXL 2.0 and PCIe Gen 5 interconnect solution. On a single 256-lane SoC, the XConn switch offers the industry’s lowest port-to-port latency and lowest power consumption per port in a single chip at a low total cost of ownership. Designed for seamless use with Samsung DRAM Memory Expander supporting CXL, XConn Apollo removes the traditional memory barriers to revolutionize memory architecture.

“Together with the CXL community, XConn is revolutionizing the memory landscape to unlock technology innovation and application performance, for generative AI as well as general cloud computing,” said Gerry Fan, CEO, XConn. “Today’s release of production silicon samples of our Apollo CXL 2.0 switch marks a new milestone in our next-generation interconnect journey. We are now empowering the realization of CXL’s promise and showing its practical use with a CXL memory pool.”

“At MemCon 2024, Samsung is excited to showcase the real-world value of CXL memory technology in action,” said Dr. Sungwook Ryu, Head of Samsung Semiconductor Memory Solutions Lab. “We strongly support the collaborative CXL ecosystem and will continue to work with CXL players to accelerate the adoption of this memory innovation. XConn CXL switch SoC chip is used in Samsung CMM-B (CXL Memory Module – Box).”

The XConn and Samsung demonstration was featured during MemCon 2024, March 26-27.

Available now in production samples, the XConn Apollo switch also supports a PCIe Gen 5 only mode for AI-intensive applications and is a key component in Open Accelerator Module (OAM), Just-a-bunch-of-GPUs (JBOG) and Just-a-Bunch-of-Accelerators (JBOA) environments. It features full support for CXL 2.0, is backwards compatible with CXL 1.1 and supports PCIe Gen 5 in hybrid mode. For more information about the XConn Apollo Switch or customer samples and/or Apollo reference boards, contact XConn here.

Related News:

Accelerating CXL Adoption with Hybrid Switch Technology

Composable Memory Solution Featured at SC23 by XConn and Liqid

The post The XConn Apollo Switch Releases Early Production Samples appeared first on Digital IT News.

CXL ensures memory coherency among CPU memory, CXL-fabric-attached memory pools, and memory on attached devices, enabling resource sharing with unparalleled performance compared to prior interconnect technologies. This breakthrough addresses the challenges faced by AI and HPC, ushering in systems capable of supporting emerging applications in AI and Machine Learning.

The Hybrid Solution for System Design Agility

While the advent of CXL instills hope for AI and HPC developers and users, system designers are still faced with how to meet both current and future interconnect requirements. PCIe (Peripheral component Interconnect Express) remains a widely used interface for connecting hardware components, including GPUs and storage devices. Many traditional applications only need the interconnect capability offered by PCIe. Yet, emergingly, next-generation applications need the higher bandwidth enabled by CXL. Systems designers can be stuck trying to meet demand for the approach with the greatest need.

XConn is meeting this challenge by offering the industry’s first and only hybrid CXL 2.0 and PCIe Gen 5 switch. Combining both interconnect technologies on a single 256-lane SoC, the XConn “Apollo” switch offers the industry’s lowest port-to-port latency and lowest power consumption per port in a single chip – all at a low total cost of ownership.

As a result, system designers only have to design once to achieve versatile expansion, heterogeneous integration for a mix of accelerators and fault tolerance with the redundancy mission critical applications required for true processing availability. Able to serve as a universal interface for CPUs, GPUs, DPUs, FPGAs, and other accelerators, the XConn hybrid switch offers:

• Versatile Expansion: CXL/PCIe switches can be used to connect multiple CXL/PCIe devices mix matched, enabling system designers to create scalable and flexible architectures. This is particularly valuable for HPC clusters and data centers where modular expansion is essential. Even more valuable is the ability to use PCIe and CXL in a single switch where system designers can design hardware once and have the flexibility to support either CXL or PCIe devices by programming the port configuration through software changes.
• Cost Efficiency: As an advanced interconnect solution, the XConn Apollo switch supports both CXL 2.0 and PCIe Gen 5 in a single system-on-chip (SoC). Offering up to 256 lanes, it offers a huge amount of switching capacity that normally requires two or more switches from other vendors – a huge cost savings for system companies on printed circuit board (PCB) area, bunch-of-memory components, and thermal consumption. The hybrid-mode design also offers design savings, where a single hardware design will work with today’s PCIe devices while being future upgradable into a CXL device without re-spinning the PCB design.
• Heterogeneous Integration: Many AI and HPC workloads require a mix of accelerators, such as GPUs, TPUs, and FPGAs. Hybrid PCIe-CXL switches can seamlessly integrate these diverse accelerators taking advantage of the processing performance, scale and lower cost of CXL memory, allowing for heterogeneous computing environments to be optimized for specific tasks.
• Fault Tolerance: The agility of hybrid PCIe-CXL switches can enhance system reliability by providing redundancy and failover capabilities. This is crucial for mission-critical applications where downtime is not an option.

CXL is transforming memory availability for AI and HPC applications. By enhancing memory bandwidth, capacity, and interoperability, CXL promises to unlock the full potential of these memory-intensive workloads. Adoption of this valuable innovation will be accelerated through the delivery of hybrid PCIe-CXL switches which deliver the versatility and efficiency systems designers need to meet diverse use case demands.

To learn more about XConn Technologies hybrid CXL switch technology, visit the website here.

Related News

CXL Ecosystem to Accelerate Due to Samsung and Red Hat Partnership Milestone

MemVerge Demonstrates How CXL Memory Expansion Will Close the Gap

The post Accelerating CXL Adoption with Hybrid Switch Technology appeared first on Digital IT News.

Memory-intensive applications such as AI and genomics research often face memory bottlenecks which can limit innovation and stall application performance. Using composable memory based on the CXL 2.0 protocol, application developers can achieve new levels of efficiency, flexibility and agility. During SC23, XConn and Liqid will showcase a composable memory solution to take processing to the next level.

Enabling the orchestration of disaggregated devices connected via CXL fabric, Liqid Matrix software now supports the XConn Apollo switch, the industry’s first and only hybrid CXL 2.0 and PCIe Gen 5 interconnect solution. On a single 256-lane SoC, the XConn switch offers the industry’s lowest port-to-port latency and lowest power consumption per port in a single chip at a low total cost of ownership. Offering integrated support for the XConn Apollo switch, Liqid Matrix composes CXL memory device endpoints to CXL connected hosts, disaggregating the memory from the host server CPU complex and connecting via CXL to a server where DRAM memory is accessed directly for applications and workloads to use with exponential efficiency.

“Next generation applications can’t be limited by traditional memory barriers. A revolutionary change must be made to today’s infrastructure architecture to empower the processing performance modern workloads need to advance,” said Gerry Fan, CEO, XConn. “Our partnership with Liqid is delivering on this need, creating truly composable memory that can meet precise memory requirements in seconds, add and remove memory in real time and truly improve memory utilization and efficiency.”

“As leading CXL innovators, XConn has developed a compelling interconnect solution for developers looking to embed the flexibility of both CXL and PCIe in a single design. This is a tremendous accelerator for CXL’s adoption,” said Sumit Puri, CEO & Co-founder of Liqid. “We are pleased to partner with XConn as we jointly deliver on the promise of CXL with composable memory for next generation applications and their workloads. Together, we are changing the memory landscape.”

“CXL memory technology, such as the composable memory solution being demonstrated by XConn and Liqid, is rapidly expanding the use of next-generation architectures,” said Jangseok (JS) Choi, vice president of New Business Planning Team at Samsung Electronics. “We are a strong supporter of the collaborative CXL ecosystem and will continue to work with significant CXL players including XConn and Liqid to accelerate the adoption of this memory innovation.”

With 256-lanes, the XConn Apollo switch also supports a PCIe Gen 5 only mode for AI-intensive applications and is a key component in Open Accelerator Module (OAM), Just-a-bunch-of-GPUs (JBOG) and Just-a-Bunch-of-Accelerators (JBOA) environments. Available now, the XConn Apollo switch features full support for CXL 2.0, is backwards compatible with CXL 1.1 and supports PCIe Gen 5 in hybrid mode.

Liqid revolutionizes the way users scale and optimize their resources with its groundbreaking Matrix composable infrastructure platform. Matrix software seamlessly integrates accelerator and storage resources into existing servers to create previously impossible resource density for the most demanding workloads.

The XConn / Liqid composable memory solution demonstration will be featured during SC23, November 12-17 in Denver. 

Related News: 

CMS Prototype with CXL 2.0 Displayed at OCP Global Summit by XConn

XConn to Demonstrate the Complete CXL 2.0 Ecosystem

The post Composable Memory Solution Featured at SC23 by XConn and Liqid appeared first on Digital IT News.

XConn Technologies (XConn) announced that it displayed a Composable Memory System ( CMS ) prototype during the 2023 OCP Global Summit, in San Jose, at the OCP Open Experience Center. The demonstration –  included solutions from AMD, Intel, MemVerge, Montage, SMART Modular, and XConn’s Apollo CXL/PCIe switch – highlighted the benefits of a Compute Express Link (CXL) 2.0-based Composable Memory System featuring memory expansion, pooling, and sharing for demanding HPC and AI applications.

The post CMS Prototype with CXL 2.0 Displayed at OCP Global Summit by XConn appeared first on Digital IT News.

The XConn Apollo Switch which supports CXL 2.0 interoperates with Samsung DRAM Memory Expander supporting CXL, Micron CZ120 memory expansion module, Memory eXpander Controller (MXC) for CXL from Montage Technology, and the high-speed CPU interconnect (CMM) for CXL from Smart Modular Technologies. The Apollo switch is the industry’s first and only hybrid CXL 2.0 and PCIe Gen 5 interconnect solution. On a single 256-lane SoC, the XConn switch offers the industry’s lowest port-to-port latency and lowest power consumption per port in a single chip at a low total cost of ownership.

“The XConn demo during Intel Innovation is the first true realization of the CXL 2.0 specification in action validating the remarkable potential of CXL as it increases memory utilization efficiency and provides true memory capacity on demand,” said Gerry Fan, CEO, XConn. “With our Apollo switch, environments can truly take advantage of CXL 2.0 to exponentially scale to support even the most memory intensive HPC and AI applications.”

The Apollo switch is a hybrid interconnect solution supporting CXL 1.1 and 2.0 as well as PCIe Gen 5 specifications in the same system. This flexibility offers system designers unprecedented flexibility to support every application need with a single chip.

“We are delighted at XConn’s contribution to the CXL ecosystem,” said Jim Pappas, director of Technology Initiatives Intel Corporation. “Their end-to-end CXL 2.0 demonstration underscores the dramatic potential of CXL to meet the increasing performance demands of next-generation data centers.”

“Samsung has collaborated with XConn in the development of advanced CXL solutions and is actively involved in the CXL 2.0 ecosystem that is architecting new memory capacity expansion solutions that optimize cost and performance for tomorrow’s most demanding applications,” said Jangseok (JS) Choi, vice president of New Business Planning Team at Samsung Electronics. “Together with XConn, we are helping the industry’s use of CXL become realized.”

“Micron and XConn have been expanding the relevance of the XConn CXL 2.0 switch features to emerging applications,” said Siva Makineni, vice president of Micron’s Advanced Memory Systems. “Our continued collaboration to lead innovative technologies underpin the impact CXL 2.0 will have in next-generation computing systems.”

“We’re pleased to see XConn bring together a complete ecosystem of CXL 2.0 innovators to illustrate the value of CXL for the future of processing,” said Larrie Carr, president, CXL Consortium.

The XConn Apollo XC50256, which features full support for CXL 2.0, is backwards compatible with CXL 1.1 and supports PCIe Gen 5 in hybrid mode, is available now. For customer samples and/or Apollo reference boards, contact XConn at the website HERE.

With 256-lanes, Apollo also supports PCIe Gen 5 mode for AI-intensive applications and is a key component for the future Intel Xeon processors in JBOG and JBOA environments.

Related News:

World’s First Hybrid CXL 2.0 and PCIe Gen5 Switch Launched by XConn

2TB Pooled CXL Memory System Unveiled by Samsung, MemVerge, H3 Platform, and XConn

The post XConn to Demonstrate the Complete CXL 2.0 Ecosystem appeared first on Digital IT News.

XConn Technologies is marking the launch of this revolutionary new XC50256 switch, code named “Apollo,” by emerging from “stealth mode” at the Flash Memory Summit.

The Apollo switch is designed from ground-up and architected purposely for artificial intelligence (AI), machine learning (ML) and HPC applications. System designs using Apollo switch can realize CXL memory pooling and expansion functions with the existing CXL 1.1 hardware today, furthermore these designs will be future proofed with the upcoming CXL 2.0 technology. Operating in hybrid mode, the switch supports both CXL and PCIe devices in a same system. This unprecedented flexibility offers system vendors to pick and choose the best components for designing an AI system, while offering a smooth transition from PCIe to CXL in a heterogenous computing environment.

“Our-record breaking Apollo switch sets a new standard in flexibility and performance for next generation of processors and memory,” said Gerry Fan, CEO, XConn. “The release of Apollo underscores our commitment to accelerate AI computing in data centers and HPC applications with the most scalable, most cost efficient and the highest-performance interconnect switch on the market. Apollo is designed to meet both PCIe and CXL requirements in a single chip. The XConn team has been and will continue to work with the industry to accelerate the adoption of CXL and advancement of AI computing.”

XConn is also announcing the availability of a PCIe Gen 5.0-only switch, XC51256. With 256-lanes, this product is the most-dense PCIe Gen 5.0 switch and offers almost twice as many lanes as the nearest competitor. This switch is ideal for the JBOG (Just-a-Bunch-Of-GPUs) and JBOA (Just-a-Bunch-Of-Accelerators) processing configurations and offers industry’s lowest latency and power while saving board space for customers by enabling usage models with a single-chip instead of multiple chips needed from competitors.

Connectivity has become the key barrier in supporting the memory bandwidth and processing speeds of data-intensive workloads such as AI/ML and genomics processing. With Apollo, XConn is breaking the bandwidth barrier by nearly doubling switch lanes delivered by competitive solutions and cutting port-to-port latency and power consumption per port by half.

“XConn is actively working in the expanding ecosystem that is accelerating CXL adoption,” said Jim Pappas, Director of Technology Initiatives, Intel Corporation. “By bridging the design gap between PCIe and CXL, advanced interconnect technologies, such as those being developed by XConn Technologies, are progressing the industry as CXL becomes the preferred standard for AI and HPC applications.”

“CXL 2.0 is the preeminent emerging technology to enable scalable memory capacity well beyond what traditional direct attached technologies support,” said Steve Pawlowski, corporate vice president of Advanced Memory Systems at Micron. “XConn’s innovative low latency CXL switch supports the creation of large, sharable memory pools across multiple servers to meet the growing demands of AI and HPC workloads. Micron is excited to continue collaborating with XConn to deliver advanced CXL solutions that will further propel the CXL ecosystem forward.”

The Apollo switch has been developed by a team of interconnect veterans that founded XConn in 2020. With decades of experience in the data center interconnect and switching field, the XConn leadership team also consists of actively contributing members of the CXL Consortium, Open Compute Project and PCI-SIG.

The XConn Apollo XC50256 and XC51256 switch samples are available now. For customer samples and/or Apollo reference boards, contact XConn at the website HERE.

Related News:

Open Storage Summit 2023 Hosted by Supermicro on August 15th

QEMU CXL Flight Simulator Introduced by MemVerge and SK hynix

The post World’s First Hybrid CXL 2.0 and PCIe Gen5 Switch Launched by XConn appeared first on Digital IT News.